RISC-V (called Risk 5) or Reduced Instruction Set Computer V is an open source instruction set developed based on the existing RISC standard for developing processing chips, and is being developed rapidly with the help of giant technology companies such as Qualcomm, Robert Bosch , Infineon and Nordic Semiconductors.
Most recently, Universiti Sains Malaysia, through the School of Electrical and Electronic Engineering (PPKEE) and has signed a memorandum of agreement to develop RISC-V technology for three years.
“We would like to thank StarFive Technology for the opportunity given, and together with us forward in driving the RISC-V ecosystem; at the same time, PPKEE will also raise awareness, foster talent and a culture of innovation related to RISC-V.” said the Dean of PPKEE, Professor Ir. Ts. Dr. Shahrel Azmin Bin Sundi @ Suandi.
These two entities will develop a controller system based on RISC-V, and for this, StarFive Technology has supplied PPKEE with twenty sets of VisionFive 2 computers, which not only house a set of RISC-V processing chips, but also with chips built-in graphics with multimedia processing capabilities, scalability, etc.
In terms of performance alone, RISC-V processing chip technology is seen to still not be comparable to ARM and X86 yet, but in terms of use in connected devices and embedded systems, RISC-V is seen to have potential in terms of development because it is based on resources open and can be developed according to the specifications and needs of the company.
Dr. Shahrel further said "We have adopted an open source model in overcoming the patent barriers of traditional architectures such as x86 and ARM and ultimately reducing the gap in developing the chip, making it a high-efficiency product that is not only low in cost, but also in terms of its power to IC market.”
